1. Field of the Invention
The present invention relates to a memory, and more particularly, it relates to a memory refreshing stored data.
2. Description of the Background Art
A ferroelectric random access memory (FeRAM) is generally known as an exemplary nonvolatile memory. The ferroelectric memory utilizes pseudo-capacitance change depending on the direction of polarization of a ferroelectric substance as a memory element. A simple matrix ferroelectric memory or a one-transistor ferroelectric memory requiring an operation of refreshing data stored in a memory cell is known as such a ferroelectric memory (refer to Japanese Patent Laying-Open No. 7-73682 (1995), for example). It is known that this simple matrix or one-transistor ferroelectric memory causes the so-called disturbance triggering data loss through reduction in the quantity of polarization of a ferroelectric capacitor resulting from a prescribed voltage applied to a memory cell connected to a word line other than a selected word line in a rewrite operation after a read operation and a write operation on a memory cell including the ferroelectric capacitor. In order to suppress this disturbance, the ferroelectric memory performs a refresh operation. The conventional ferroelectric memory disclosed in the aforementioned Japanese Patent Laying-Open No. 7-73682 counts the frequency of external access operations, for performing a refresh operation when the access frequency reaches a constant number of times.
On the other hand, a technique for performing a refresh operation uncompetitively with an internal access operation is generally proposed in relation to a memory performing the refresh operation (refer to Japanese Patent Laying-Open No. 2001-229674, for example). Japanese Patent Laying-Open No. 2001-229674 discloses a DRAM (dynamic random access memory) performing an internal access operation (read or write operation) in synchronization with an internal clock having a shorter cycle than an external clock having a prescribed cycle. In general, a DRAM must perform a refresh operation after a lapse of a prescribed period. In the DRAM disclosed in Japanese Patent Laying-Open No. 2001-229674, the number of internal clocks generated in a constant period is larger than that of external clocks input in this constant period since the cycle of the internal clock is shorter than that of the external clock. Thus, this DRAM cyclically generates an internal clock also when no external access operation is performed in synchronization with an external clock, to result in periodic generation of an internal clock triggering no internal access operation corresponding to an external access operation. Therefore, the DRAM disclosed in Japanese Patent Laying-Open No. 2001-229674 performs a refresh operation in synchronization with the internal clock triggering no internal access operation.
However, the conventional DRAM disclosed in the aforementioned Japanese Patent Laying-Open No. 2001-229674 renders the cycle of the internal clock for performing the internal access operation shorter than that of the external clock on the premise that the external access operation is cyclically performed in synchronization with the external clock, thereby cyclically generating an internal clock triggering no internal access operation and performing a refresh operation in synchronization with this internal clock triggering no internal access operation. In other words, the technique disclosed in Japanese Patent Laying-Open No. 2001-229674 is applicable to a memory subjected to an external access operation cyclically performed in synchronization with an external clock, since this memory can cyclically generate an internal clock triggering no internal access operation. However, a memory subjected to an non-cyclically performed external access operation cannot cyclically generate an internal clock triggering no internal access operation since the period of the external access operation is not constant. Consequently, the technique of Japanese Patent Laying-Open No. 2001-229674 performing the refresh operation uncompetitively with the internal access operation cannot be applied to a memory subjected to a non-cyclically performed external access operation.